View GD25Q32_8292038.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

GD25Q32c datasheet http://www.elm-tech.com
2 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash - content - page 1. f eatures --------------------------- --------------------------- ---------------------------- - -------------- 4 2. general description ------------------------------------------------------ - ---------------------- 5 3. memory organization --------------------------------------------------------- - ---------------- 6 4. device operation ----------------------------------------------------------------- - - - - - - - - - ------ - - 7 5. data protection ----------------------------------------------------------------------- - - - - - ------- - 8 6. status register -------------------------------------------------------------- - - - - - - - - - - - - - - - ------- - 10 7. commands description ------------------------------------------- --- - - - - - - - - - - - - - - - - - --------- - 1 2 7.1. write enable (wren) (06h) ---------------------------------------------------- - - - - - - - - - - - - ------- 1 5 7.2. write disable (wrdi) (04h) ------------------------------------------------------------- - - - - - - - - - - 1 5 7.3. write enable for volatile status register (50h) ---------- ---------- -------------- ------- ----- - - -- 1 5 7.4. read status register (rdsr) (05h or 35h or 15h) ------------------------------------ - ------- 1 6 7.5. write status register (wrsr) (01h or 31h or 11h) ---------- ---- -------- ------- -- - - - - - - - ----- 1 6 7.6. read data bytes (read) (03h) ------------------------------------------------ - - - - - - - - - - - - - ------- 1 7 7.7. read data bytes at higher speed (fast read) (0bh) ---------------------- - - - - - - - - - - - - - - ------- 1 7 7.8. dual output fast read (3bh) --------------------------------------------------------- - - - - - - - ------ 1 8 7.9. quad output fast read (6bh) ------------------------------------ ---------------------------------- 1 9 7.10. dual i/o fast read (bbh) ------------------------------------------------------------------ - - - - --- 1 9 7.11. quad i/o fast read (ebh) ------------------------------------------------------ - - - - - - - - - - - - - ------ 20 7.12. quad i/o word fast read (e7h) ------------------------------------------------------------------ 2 2 7. 1 3 . set burst with wrap (77h) ---------------------------------------------------------------- - - - - - - --- - 23 7.14. page program (pp) (02h) - -------------------------------------------------------------------------- 24 7.15. quad page program (32h) ---------- ---------------------- --------------------- ----- ----- - - - - ------- 2 5 7.16 fast page program (fpp) (f2h) -------------------------------- --------------------- ----- --------- - 26 7.17. sector erase (se) (20h) ---------- ------------------------------------------------ - - - - - - - - - - - - ------- 2 7 7.18. 32kb block erase (be) (52h) --------------------------------------------------------------------- 2 8 7.19. 64kb block erase (be) (d8h) ------------------------------------------------------ - - - - - - - - - ------ 2 8 7.20. chip erase (ce) (60/c7h) ---------- ---------------- -------------- ------- --- --- --- --- --- - - - - - - - - - --- 2 9 7.2 1 . deep power-down (dp) (b9h) ---------------------------------------------------------------- - --- - 2 9 7.22. release from deep power-down or high performance mode and read device id (rdi) (abh) 30 7.23. read manufacture id/device id (rems) (90h) ---------- -------- -------------- - --- ----- - ------- 3 1 7.24. dual i/o read manufacture id/device id (92h) ---------- -------- ----- -- --- --- --- -- - - --- - ------ 3 2 7.25. quad i/o read manufacture id/device id (94h) ---- -- -------------- ------- --- --- - - -- --- --- ---- 3 2 7.2 6 . read identification (rdid) (9fh) ------------------------------------------------------------- - --- - 3 3
3 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7.27. high performance mode (hpm) (a3h) --------------------------------------------- - - - - - - - - - ----- 34 7.28 . program/erase suspend (pes) (75h) ---- ----------------------------- --- --- --- --- --- ---- ---------- 3 4 7. 29 . program/erase resume (per) (7ah) --------------------------------------------------------- - --- - 3 5 7.30. erase security registers (44h) -------------------------------- ------------------------------- ------- 3 5 7.31. program security registers (42h) ---------------------------------- ------- ------- ------- ---- ------- 3 6 7.32. read security registers (48h) -------------------------------- ------ ------ ------ ------ ------ -------- 3 7 7. 33 . enable reset (66h) and reset (99h) --------------------------------------------------------- - - --- - 3 8 7. 3 4 . read serial flash discoverable parameter (5ah) ------------------------------------------- - --- - 3 8 8 . electrical characteristics ------------------------------------------- - ------------------- 4 3 8 .1. power- on timing ------------------------------------------------------------------------------------- 4 3 8 .2. initial delivery state ---------------------------------------------------------------------------------- 4 3 8 .3. data retention and endurance ----------------------------------------------------------------------- 4 3 8 .4. abso lute maximum ratings ------------------------------------------------------------------------- 44 8 . 5 . capacitance measurement co nditions -------------------------------------------------------- - --- - 44 8 .6. dc characteristics ----------------------------------------------------------------------------------- 4 5 8 .7. a c characteristics --------------------------------------------------------------------------- -------- 4 5 9 . ordering information --------------------------------------------------- --------------------- - 4 8 10 . package information ------------------------------------------- ------------------------------- - 4 9 10 .1. package sop8 208mil ------------------------------------------------ ------------------------- ---- 4 9 10 .2. package wson8 (6 5mm) ------------------------------------------ ------------------------- - ---- 50
4 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 1. features ? 3 2m-bit serial flash - 4096k-byte - 256 bytes per programmable page ? standard, dual, quad spi - standard spi: sclk, cs#, si, so, wp#, hold# - dual spi: sclk, cs#, io0, io1, wp#, hold# - quad spi: sclk, cs#, io0, io1, io2, io 3 ? high speed clock frequency - 120mhz for fast read with 30pf load - dual i/o data transfer up to 240mbits/s - quad i/o data transfer up to 480mbits/s - continuous read with 8/16/32/64-byte wrap ? software/hardware write protection - w rite protect all/portion of memory via software - enable/disable protection with wp# pin - top or bottom, sector or block selection ? cycling endurance - minimum 100,000 program/erase cycles ? data retention - 20-year data retention typical . note: (1) please contact elm for details. ? program/erase speed - page program time: 0.6ms typical - sector erase time: 50ms typical - block e rase time: 0.15/0.25s typical - chip e rase time: 15s typical ? flexible architecture - sector of 4k-byte - block of 32/64k-byte ? low power consumption - 20 ma maximum active current - 5a maximum power down current ? advanced security features (1) - 31024-byte security registers with otp locks - discoverable parameters(sfdp) register ? single power supply voltage - full voltage range: 2.7~3.6v ? package information - sop8 (208mil) - wson8 ( 6 5 mm) http://www.elm-tech.com
5 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 2. general description the GD25Q32c(32m-bit) serial flash supports the standard serial peripheral interface (spi), and supports the dual/quad spi: serial clock, chip select, serial data i/o0 (si), i/o1 (so), i/o2 (wp#) and i/o3 (hold#). the dual i/o data is transferred with speed of 240mbits/s and the quad i/o & quad output data is transferred with speed of 480mbits/s. connection diagram 8-lead sop 8-lead wso n pin name i / o description cs# i chip select input so (io1) i/o data output (data input output 1) wp# (io2) i/o write protect input (data input output 2) vss ground si (io0) i/o data input (data input output 0) sclk i serial clock input hold# (io3) i/o hold input (data input output 3) vcc power supply pin description spi command & control logic high voltage generators page address latch / counter status register write control logic byte address latch / counter column decode and 256 - byte page buffer write protect logic and row decode flash memory cs # sclk si( io 0) so( io 1) hold #( io 3) wp #( io 2) block diagram
6 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash http://www.elm-tech.com each device has each block has each sector has each page has 4m 64/32k 4k 256 bytes 16k 256/128 16 - pages 1024 16/8 - - sectors 64 /128 - - - blocks 3. memory organization GD25Q32c GD25Q32c 64k bytes block sector architecture block sector address range 63 1023 3f f000h 3f ffffh ----- ----- ----- 1008 3f 0000h 3f 0fffh 62 1007 3e f000h 3e ffffh ----- ----- ----- 992 3e 0000h 3e 0fffh ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- 2 47 02f000h 02ffffh ----- ----- ----- 32 020000h 020fffh 1 31 01f000h 01ffffh ----- ----- ----- 16 010000h 010fffh 0 15 00f000h 00ffffh ----- ----- ----- 0 000000h 000fffh uniform block sector architecture
7 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 4 . device operation spi mode standard spi the GD25Q32c feature a serial peripheral interface on 4 signals bus: serial clock (sclk), chip select (cs#), serial data input (si) and serial data output (so). both spi bus mode 0 and 3 are supported. input data is latched on the rising edge of sclk and data shifts out on the falling edge of sclk. dual spi the GD25Q32c supports dual spi operation when using the dual output fast read (3bh), dual i/o fast read (bbh) and read manufacture id/device id dual i/o (92h) commands. these commands allow data to be transferred to or from the device at two times the rate of the standard spi. when using the dual spi command the si and so pins become bidirectional i/o pins: io0 and io1. quad spi the GD25Q32c supports quad spi operation when using the quad output fast read(6bh), quad i/o fast read(ebh), quad i/o word fast read(e7h), read manufacture id/device id quad i/o (94h) and quad page program (32h) commands. these commands allow data to be transferred to or from the device at four times the rate of the standard spi. when using the quad spi command the si and so pins become bidirectional i/o pins: io0 and io1, and wp# and hold# pins become io2 and io3. quad spi commands require the non- volatile quad enable bit (qe) in status register to be set. hold the hold# function is only available when qe=0, if qe=1, the hold# function is disabled, the pin acts as dedicated data i/o pin. t he hold# signal goes low to stop any serial communications with the device, but doesn t stop the operation of write status register , programming, or erasing in progress. the operation of hold, need cs# keep low, and starts on falling edge of the hold# signal, with sclk signal being low (if sclk is not being low, hold operation will not start until sclk being low). the hold condition ends on rising edge of hold# signal with sclk being low (if sclk is not being low, hold operation will not end until sclk being low). the so is high impedance, both si and sclk dont care during the hold operation, if cs# drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and then cs# must be at low. figure 1. hold condition hold hold cs # sclk hold #
8 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 5 . data protection the GD25Q32c provides the following data protection methods: ? write enable (wren) command: the wren command is set the write enable latch bit (wel). the wel bit will return to reset by the following situation: - power-up - write disable (wrdi) - write status register (wrsr) - page program (pp) - sector erase (se) / block erase (be) / chip erase (ce) ? software protection mode: the block protect (bp4, bp3, bp2, bp1 and bp0) bits define the section of the memory array that can be read but not change. ? hardware protection mode: wp# going low to protected the bp0~bp4 bits and srp0~1 bits. ? deep power-down mode: in deep power-down mode, all commands are ignored except the release from deep power-down mode command. status register content memory content bp4 bp3 bp2 bp1 bp0 blocks addresses density portion 0 0 0 none none none none 0 0 0 0 1 63 3 f0 000h-3fffffh 64kb upper 1/64 0 0 0 1 0 62 to 63 3 e 0 000h-3fffffh 128 kb upper 1/ 32 0 0 0 1 1 60 to 63 3 c 0 000h-3fffffh 256 kb upper 1/ 16 0 0 1 0 0 56 to 63 3 8 0 000h-3fffffh 512 kb upper 1/ 8 0 0 1 0 1 48 to 63 3 0 0 000h-3fffffh 1mb upper 1/ 4 0 0 1 1 0 32 to 63 200000h-3fffffh 2mb upper 1/ 2 0 1 0 0 1 0 000000h-00ffffh 64 kb lower 1/64 0 1 0 1 0 0 to 1 000000h-01ffffh 128 kb lower 1/32 0 1 0 1 1 0 to 3 000000h-03ffffh 256 kb lower 1/16 0 1 1 0 0 0 to 7 000000h-07ffffh 512k b lower 1/8 0 1 1 0 1 0 to 15 000000h-0fffffh 1m b lower 1/4 0 1 1 1 0 0 to 31 000000h-1fffffh 2mb lower 1/ 2 1 1 1 0 to 63 0 00 000h-3fffffh 4 m b all 1 0 0 0 1 63 3 f f0 00h-3fffffh 4 kb top block 1 0 0 1 0 63 3fe000h- 3fffffh 8 kb top block 1 0 0 1 1 63 3fc000h- 3fffffh 16 k b top block 1 0 1 0 63 3f8000h- 3fffffh 32kb top block 1 0 1 1 0 63 3f8 000h-3fffffh 32 kb top block 1 1 0 0 1 0 000000h-000fffh 4 kb bottom block 1 1 0 1 0 0 000000h-001fffh 8 kb bottom block 1 1 0 1 1 0 000000h-003fffh 16 kb bottom block 1 1 1 0 0 000000h-007fffh 32kb bottom block 1 1 1 1 0 0 000000h-007fffh 32 kb bottom block table1.0 GD25Q32c protected area size (cmp=0)
9 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash status register content memory content bp4 bp3 bp2 bp1 bp0 blocks addresses density portion 0 0 0 all 000000h-3fffffh 4m b all 0 0 0 0 1 0 to 62 000000h-3effffh 403 2 kb lower 63/64 0 0 0 1 0 0 to 61 000000h-3dffffh 3968 kb lower 31/32 0 0 0 1 1 0 to 59 000000h-3bffffh 3840 kb lower 15/ 16 0 0 1 0 0 0 to 55 000000h-37ffffh 3584 k b lower 7/ 8 0 0 1 0 1 0 to 47 000000h-2fffffh 3mb lower 3/ 4 0 0 1 1 0 0 to 31 000000h-1fffffh 2 m b lower 1/2 0 1 0 0 1 1 to 63 010000h-3fffffh 4032kb u pper 63 /64 0 1 0 1 0 2 to 63 020000h-3fffffh 3968kb u pper 31 / 32 0 1 0 1 1 4 to 63 040000h-3fffffh 3840kb u pper 15 / 16 0 1 1 0 0 8 to 63 080000h-3fffffh 3584kb u pper 7 / 8 0 1 1 0 1 16 to 63 100000h-3fffffh 3mb u pper 3 / 4 0 1 1 1 0 32 to 63 200000h-3fffffh 2mb u pper 1 / 2 1 1 1 none none none none 1 0 0 0 1 0 to 6 3 000000h-3fefffh 4092 kb l-1023/1024 1 0 0 1 0 0 to 6 3 000000h-3fdfffh 408 8 kb l-511/512 1 0 0 1 1 0 to 6 3 000000h-3fbfffh 4080 kb l-255/ 25 6 1 0 1 0 0 to 6 3 000000h-3f7fffh 4064 kb l-127/12 8 1 0 1 1 0 0 to 63 000000h-3f7fffh 4064 kb l-127/12 8 1 1 0 0 1 0 to 6 3 001000h-3fffffh 4092 kb u -1023 /1024 1 1 0 1 0 0 to 6 3 002000h-3fffffh 4088 kb u -511/512 1 1 0 1 1 0 to 6 3 004000h-3fffffh 4 080kb u -255/ 25 6 1 1 1 0 0 to 6 3 008000h-3fffffh 4064 kb u -127/12 8 1 1 1 1 0 0 to 63 008000h-3fffffh 4064 kb u -127/12 8 table1.1. GD25Q32c protected area size (cmp=1)
10 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 6 . status register the status and control bits of the status register are as fo llows: w ip bit. the write in progress (wip) bit indicates whether the memory is busy in program/erase/write status register progress. when wip bit sets to 1, means the device is busy in program/erase/write status register progress, when wip bit sets 0, means the device is not in program/erase/write status register progress. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase command is accepted. bp4, bp3, bp2, bp1, bp 0 bits. the block protect (bp4, bp3, bp2, bp1 and bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase commands. these bits are written with the write status register (wrsr) command. when the block protect (bp4, bp3, bp2, bp1 and bp0) bits are set to 1, the relevant memory area (as defined in table1). becomes protected against page program (pp), sector erase (se) and block erase (be) commands. the block protect (bp4, bp3, bp2, bp1 and bp0) bits can be written provided that the hardware protected mode has not been set. the chip erase (ce) command is executed, only if the block protect (bp2, bp1 and bp0) bits are 0 and cmp=0. srp1, srp0 bits. the status register protect (srp1 and srp0) bits are non-volatile read/write bits in the status register. the srp bits control the method of write protection: software protection, hardware protection, power supply lock- down or one time programmable protection. s15 s14 s13 s12 s11 s10 s9 s8 sus1 cmp lb3 lb2 lb1 sus2 qe srp1 s7 s6 s5 s4 s3 s2 s1 s0 srp0 bp4 bp3 bp2 bp1 bp0 wel wip srp1 srp 0 #wp status register description 0 0 software protected the status register can be written to after a write enable command, wel=1.(default) 0 1 0 hardware protected wp#=0, the status register locked and can not be written to. 0 1 1 hardware unprotected wp#=1, the status register is unlocked and can be written to after a write enable command, wel=1. 1 0 power supply lock-down(1) status register is protected and can not be written to again until the next power-down, power-up cycle. 1 1 one time program(2) status register is permanently protected and can not be written to. s23 s22 s21 s20 s19 s18 s17 s16 reserved drv1 drv0 hpf reserved reserved reserved reserved
11 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash note: (1). when srp1, srp0= (1, 0), a power-down, power-up cycle will change srp1, srp0 to (0, 0) state. (2). this feature is available on special order. (GD25Q32cxxsx)please contact elm for details. qe bit. the quad enable (qe) bit is a non-volatile read/write bit in the status register that allows quad operation. when the qe bit is set to 0 (default) the wp# pin and hold# pin are enable. when the qe pin is set to 1, the quad io2 and io3 pins are enabled. (the qe bit should never be set to 1 during standard spi or dual spi operation if the wp# or hold# pins are tied directly to the power supply or ground). lb3, lb2, lb1 bits. the lb3, lb2, lb1 bits are non-volatile one time program (otp) bits in status register (s13-s11) that provide the write protect control and status to the security registers. the default state of lb3-lb1 are 0, the security registers are unlocked. the lb3-lb1 bits can be set to 1 individually using the write register instruction. the lb3-lb1 bits are one time programmable, once its set to 1, the security registers will become read-only permanently. cmp bit. the cmp bit is a non-volatile read/write bit in the status register (s14). it is used in conjunction the bp4- bp0 bits to provide more flexibility for the array protection. please see the status registers memory protection table for details. the default setting is cmp=0. sus1, sus2 bits. the sus1 and sus2 bits are read only bit in the status register (s15 and s10) that are set to 1 after executing an program/ erase suspend (75h) command (the erase suspend will set the sus1 to 1, and the program suspend will set the sus2 to 1) . the sus1 and sus2 bits are cleared to 0 by program/ erase resume (7ah) command as well as a power-down, power-up cycle. hpf bit. the high performance flag (hpf) bit indicates the status of high performance mode (hpm). when hpf bit sets to 1, it means the device is in high performance mode, when hpf bit sets 0 (default), it means the device is not in high performance mode. drv1/drv0 . the drv1 & drv0 bits are used to determine the output driver strength for the read operations. drv 1, drv0 driver strength 00 100% 01 75% (default) 10 50% 11 25%
12 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7. commands description all commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of sclk after cs# is driven low. then, the one-byte command code must be shifted in to the device, most significant bit first on si, each bit being latched on the rising edges of sclk. see table2, every command sequence starts with a one-byte command code. depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. cs# must be driven high after the last bit of the command sequence has been shifted in. for the command of read, fast read, read status register or release from deep power-down, and read device id, the shifted-in command sequence is followed by a data- out sequence. cs# can be driven high after any bit of the data-out sequence is being shifted out. for the command of page program, sector erase, block erase, chip erase, write status register, write enable, write disable or deep power-down command, cs# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. that means cs# must be driven high when the number of clock pulses after cs# being driven low is an exact multiple of eight. for page program, if cs# is driven high at any time the input byte is not a full byte, nothing will happen and wel will not be reset. command name byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h volatile sr write enable 50h read status register-1 05h (s7-s0) (continuous) read status register-2 3 5h (s15-s8) (continuous) read status register- 3 15h (s23-s16) (continuous) write status register-1 01h s7-s0 write status register-2 3 1h s15-s8 write status register- 3 11h s23-s16 read data 03h a23-a16 a15-a8 a7-a0 (d7-d0) (next byte) (continuous) fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) (continuous) dual output fast read 3bh a23-a16 a15-a8 a7-a0 dummy d7-d0 (1) (continuous) dual i/o fast read bbh a23 -a8 (2) a7-a0 m7 -m0 (2) (d7-d0) (1) (next byte) (next byte) (continuous) quad output fast read 6bh a23-a16 a15-a8 a7-a0 dummy (d7 -d0) (3) (continuous) quad i/o fast read ebh a23-a0 m7 -m0 (4) dummy (5) (d7-d0) (3) (next byte) (next byte) (continuous) quad i/o word fast read (7) e7h a23-a0 m7 -m0 (4) dummy (6) (d7-d0) (3) (next byte) (next byte) (continuous) page program 02h a23-a16 a15-a8 a7-a0 d7-d0 next byte continuous quad page program 32h a23-a16 a15-a8 a7-a0 d7-d0 (3) next byte continuous fast page program f2h a23-a16 a15-a8 a7-a0 d7-d0 next byte continuous sector erase 20h a23-a16 a15-a8 a7-a0 block erase (32k) 52h a23-a16 a15-a8 a7-a0 block erase (64k) d8h a23-a16 a15-a8 a7-a0 chip erase c7/60h enable reset 66h reset 99h table2. commands (standard/dual/quad spi)
13 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash command name byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes set burst with wrap 77h dummy (9) w7-w0 program/erase suspend 75h program/erase resume 7ah release from deep power-down, and read device id abh dummy dummy dummy (did7- did0) (continuous) release from deep power-down abh deep power-down b9h manufacturer/ device id 90h dummy dummy 00h (mid7- mid0) (did7- did0) (continuous) manufacturer/ device id by dual i/o 92h a23-a8 a7-a0, m7-m0 (mid7-mid0) (did7-did0) (continuous) manufacturer/ device id by quad i/o 94h a23-a0, m7-m0 dummy (10) (mid7- mid0) (did7-did0) (continuous) read identification 9fh (mid7- mid0) (jdid15- jdid8) (jdid7- jdid0) (continuous) high performance mode a3h dummy dummy dummy read serial flash discoverable parameter 5ah a23-a16 a15-a8 a7-a0 dummy (d7-d0) (continuous) erase security registers (8) 44h a23-a16 a15-a8 a7-a0 program security registers (8) 42h a23-a16 a15-a8 a7-a0 d7-d0 d7-d0 continuous read security registers (8) 48h a23-a16 a15-a8 a7-a0 dummy (d7-d0) (continuous) note: (1) dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) (2) dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 (3) quad output data io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3, ..)
14 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash table of id definitions: gd25q 32c operation code mid7-mid0 id15-id8 id7-id0 9fh c8 40 16 90h/92h/94h c8 15 abh 15 (4) quad input address io0 = a20, a16, a12, a8, a4, a0, m4, m0 io1 = a21, a17, a13, a9, a5, a1, m5, m1 io2 = a22, a18, a14, a10, a6, a2, m6, m2 io3 = a23, a19, a15, a11, a7, a3, m7, m3 (5) fast read quad i/o data io0 = (x, x, x, x, d4, d0,) io1 = (x, x, x, x, d5, d1,) io2 = (x, x, x, x, d6, d2,) io3 = (x, x, x, x, d7, d3,) (6) fast word read quad i/o data io0 = (x, x, d4, d0,) io1 = (x, x, d5, d1,) io2 = (x, x, d6, d2,) io3 = (x, x, d7, d3,) (7) fast word read quad i/o data: the lowest address bit must be 0. (8) security registers address: security register1: a23-a16=00h, a15-a10=000100b, a9-a0=byte address; security register2: a23-a16=00h, a15-a10=001000b, a9-a0=byte address; security register3: a23-a16=00h, a15-a10=001100b, a9-a0=byte address. (9) dummy bits and wrap bits io0 = (x, x, x, x, x, x, w4, x) io1 = (x, x, x, x, x, x, w5, x) io2 = (x, x, x, x, x, x, w6, x) io3 = (x, x, x, x, x, x, w7, x) (10) address, continuous read mode bits, dummy bits, manufacture id and device id io0 = (a20, a16, a12, a8, a4, a0, m4, m0, x, x, x, x, mid4, mid0, did4, did0, ) io1 = (a21, a17, a13, a9, a5, a1, m5, m1, x, x, x, x, mid5, mid1, did5, did1, ) io2 = (a22, a18, a14, a10, a6, a2, m6, m2, x, x, x, x, mid6, mid2, did6, did2, ) io3 = (a23, a19, a15, a11, a7, a3, m7, m3, x, x, x, x, mid7, mid3, did7, did3, )
15 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7.1 . write enable (wren)(06h) the write enable (wren) command is for setting the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), block erase (be), chip erase (ce), write status register (wrsr) and erase/ program security register command. the write enable (wren) command sequence: cs# goes low sending the write enable command cs# goes high. command 0 1 2 3 4 5 6 7 06h cs# sclk si so high-z 7.2. write disable (wrdi) (04h) the write disable command is for resetting the write enable latch (wel) bit. the write disable command sequence: cs# goes low sending the write disable command cs# goes high. the wel bit is reset by following condition: power-up and upon completion of the write status register, page program, sector erase, block erase, chip erase, erase/ program security register and reset commands. command 0 1 2 3 4 5 6 7 04h cs# sclk si so high-z 7.3 . write enable for volatile status register (50h) the non-volatile status register bits can also be written to as volatile bits. this gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non- volatile bit write cycles or affecting the endurance of the status register non-volatile bits. the write enable for volatile status register command must be issued prior to a write status register command. the write enable for volatile status register command will not set the write enable latch bit, it is only valid for the write status register command to change the volatile status register bit values. figure 2. write enable sequence diagram figure 3. write disable sequence diagram
16 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 4. write enable for volatile status register sequence diagram cs# sclk command(50h) si so 0 1 2 3 4 5 6 7 high -z 7.5. write status register (wrsr) (01h or 31h or 11h) the write status register (wrsr) command allows new values to be written to the status register. before it can be accepted, a write enable (wren) command must previously have been executed. after the write enable (wren) command has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) command has no effect on s23, s20, s19, s18, s17, s16, s15, s10, s1 and s0 of the status register. cs# must be driven high after the eighth of the data byte has been latched in. if not, the write status register (wrsr) command is not executed. as soon as cs# is driven high, the self- timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) command allows the user to change the values of the block protect (bp4, bp3, bp2, bp1 and bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table1. the write status register (wrsr) command also allows the user to set or reset the status register 7.4. read status register (rdsr) (05h or 35h or 15h) the read status register (rdsr) command is for reading the status register. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new command to the device. it is also possible to read the status register continuously. for command code 05h 35h 15h, the so will output status register bits s7~s0 / s15~s8 / s16~s23. figure 5. read status register sequence diagram
17 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash protect (srp1 and srp0) bits in accordance with the write protect (wp#) signal. the status register protect (srp1 and srp0) bits and write protect (wp#) signal allow the device to be put in the hardware protected mode. the write status register (wrsr) command is not executed once the hardware protected mode is entered. figure 6. write status register sequence diagram 7.6. read data bytes (read) (03h) the read data bytes (read) command is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency f r , during the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) command. any read data bytes (read) command, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 7. read data bytes sequence diagram command 0 1 2 3 4 5 6 7 03 h cs # sclk si so high -z 8 9 10 28 29 30 31 32 msb 3 2 1 0 34 35 36 37 33 23 22 21 7 6 5 4 3 2 1 0 38 39 24 - bit address msb data out 1 data out 2 7.7. read data bytes at higher speed (fast read) (0bh) the read data bytes at higher speed (fast read) command is for quickly reading data out. it is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency f c , during the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out.
18 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 8. read data bytes at higher speed sequence diagram 7. 8 . dual output fast read (3bh) the dual output fast read command is followed by 3-byte address (a23-a0) and a dummy byte, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 2-bit per clock cycle from si and so. the command sequence is shown in followed figure9. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 9. dual output fast read sequence diagram
19 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7. 9 . quad output fast read (6bh) the quad output fast read command is followed by 3-byte address (a23-a0) and a dummy byte, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 4-bit per clock cycle from io3, io2, io1 and io0. the command sequence is shown in followed figure10. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 10. quad output fast read sequence diagram command 0 1 2 3 4 5 6 7 6bh cs # sclk si( io 0) so( io 1) high -z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address 34 35 36 37 33 1 5 1 5 1 5 1 38 39 byte1 32 42 43 44 45 41 46 47 40 5 dummy clocks 0 4 0 4 0 4 0 4 4 5 wp #( io 2) high -z hold #( io 3) high -z cs # sclk si( io 0) so( io 1) wp #( io 2) hold #( io 3) 2 6 2 6 2 6 2 6 6 3 7 3 7 3 7 3 7 7 byte2 byte3 byte4 7. 1 0 . dual i/o fast read (bbh) the dual i/o fast read command is similar to the dual output fast read command but with the capability to input the 3-byte address (a23-0) and a continuous read mode byte 2-bit per clock by si and so, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 2-bit per clock cycle from si and so. the command sequence is shown in followed figure11. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. dual i/o fast read with continuous read mode the dual i/o fast read command can further reduce command overhead through setting the continuous read mode bits (m7-4) after the input 3-byte address (a23-a0). if the continuous read mode bits (m5-4) =(1, 0), then the next dual i/o fast read command (after cs# is raised and then lowered) does not require the bbh command code. the command sequence is shown in followed figure12. if the continuous read mode bits (m5-4) do not equal (1, 0), the next command requires the first bbh command code, thus returning to normal operation. a continuous read mode reset command can be used to reset (m5-4) before issuing normal command.
20 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 11. dual i/o fast read sequence diagram (m5-4 (1, 0)) figure 11. dual i/o fast read sequence diagram (m5-4 ? (1, 0)) figure 12. dual i/o fast read sequence diagram (m5-4 = (1, 0)) figure 12. dual i/o fast read sequence diagram (m5-4= (1, 0)) 7. 1 1 . quad i/o fast read (ebh) the quad i/o fast read command is similar to the dual i/o fast read command but with the capability to input the 3-byte address (a23-0) and a continuous read mode byte and 4-dummy clock 4-bit per clock by io0, io1, io2, io3, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 4-bit per clock cycle from io0, io1, io2, io3. the command sequence is shown in followed figure13. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the quad enable bit (qe) of status register (s9) must be set to enable for the quad i/o fast read command.
21 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash quad i/o fast read with continuous read mode the quad i/o fast read command can further reduce command overhead through setting the continuous read mode bits (m7-0) after the input 3-byte address (a23-a0). if the continuous read mode bits (m5-4) =(1, 0), then the next quad i/o fast read command (after cs# is raised and then lowered) does not require the ebh command code. the command sequence is shown in followed figure14. if the continuous read mode bits (m5-4) do not equal to (1, 0), the next command requires the first ebh command code, thus returning to normal operation. a continuous read mode reset command can be used to reset (m5-4) before issuing normal command. figure 13. quad i/o fast read sequence diagram (m5-4 (1, 0)) command 0 1 2 3 4 5 6 7 ebh cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 a 23 - 16 a 15 -8 a7-0 m7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 wp #( io 2) hold #( io 3) 4 5 6 7 dummy byte1 byte2 figure 14. quad i/o fast read sequence diagram ( m5-4 = (1, 0) ) 0 1 2 3 4 5 6 7 cs # sclk 8 9 10 11 12 13 14 15 si( io 0) so( io 1) wp #( io 2) hold #( io 3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 a 23 - 16 a 15 -8 a7-0 m7-0 dummy byte1 byte2 quad i/o fast read with 8/16/32/64-byte wrap around in standard spi mode the quad i/o fast read command can be used to access a specific portion within a page by issuing set burst with wrap (77h) commands prior to ebh. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following ebh commands. when wrap around is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. the output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until cs# is pulled high to terminate the command.
22 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. the set burst with wrap command allows three wrap bits w6-w4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6-w5 is used to specify the length of the wrap around section within a page. 7. 1 2 . quad i/o word fast read (e7h) the quad i/o word fast read command is similar to the quad i/o fast read command except that the lowest address bit (a0) must equal 0 and only 2-dummy clock. the command sequence is shown in followed figure15. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the quad enable bit (qe) of status register (s9) must be set to enable for the quad i/o word fast read command. quad i/o word fast read with continuous read mode the quad i/o word fast read command can further reduce command overhead through setting the continuous read mode bits (m7-0) after the input 3-byte address (a23-a0). if the continuous read mode bits (m5-4) =(1, 0), then the next quad i/o word fast read command (after cs# is raised and then lowered) does not require the e7h command code. the command sequence is shown in followed figure16. if the continuous read mode bits (m5-4) do not equal to (1, 0), the next command requires the first e7h command code, thus returning to normal operation. a continuous read mode reset command can be used to reset (m5-4) before issuing normal command. figure 15. quad i/o word fast read sequence diagram (m5-4 (1, 0) ) command 0 1 2 3 4 5 6 7 e7h cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 a 23 - 16 a 15 -8 a7-0 m7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 wp #( io 2) hold #( io 3) 4 5 6 7 dummy byte1 byte2 4 0 5 1 6 2 7 3 byte3
23 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 16. quad i/o word fast read sequence diagram ( m5-4 = (1, 0) ) 0 1 2 3 4 5 6 7 cs # sclk 8 9 10 11 12 13 14 15 si( io 0) so( io 1) wp #( io 2) hold #( io 3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 a 23 - 16 a 15 -8 a7-0 m7-0 dummy byte1 byte2 4 0 5 1 6 2 7 3 byte3 quad i/o word fast read with 8/16/32/64-byte wrap around in standard spi mode the quad i/o word fast read command can be used to access a specific portion within a page by issuing set burst with wrap (77h) commands prior to e7h. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following e7h commands. when wrap around is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. the output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until cs# is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. the set burst with wrap command allows three wrap bits w6-w4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6-w5 is used to specify the length of the wrap around section within a page. 7. 1 3 . set burst with wrap (77h) the set burst with wrap command is used in conjunction with quad i/o fast read and quad i/o word fast read command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard spi mode. the set burst with wrap command sequence: cs# goes low send set burst with wrap command send 24 dummy bits send 8 bits wrap bits cs# goes high. w6, w5 w4=0 w4=1 (default) wrap around wrap length wrap around wrap length 0, 0 yes 8-byte no n/a 0, 1 yes 16 -byte no n/a 1, 0 yes 32 -byte no n/a 1, 1 yes 64 -byte no n/a if the w6-w4 bits are set by the set burst with wrap command, all the following quad i/o fast read and quad i/o word fast read command will use the w6-w4 setting to access the 8/16/32/64-byte section within any page. to exit the wrap around function and return to normal read operation, another set burst with wrap command should be issued to set w4=1.
24 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7. 1 4 . page program (pp) (02h) the page program (pp) command is for programming the memory. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the page program (pp) command is entered by driving cs# low, followed by the command code, three address bytes and at least one data byte on si. if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). cs# must be driven low for the entire duration of the sequence. the page program command sequence: cs# goes low sending page program command 3-byte address on si at least 1 byte data on si cs# goes high. the command sequence is shown in figure18. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the page program (pp) command is not executed. as soon as cs# is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) command applied to a page which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) is not executed. figure 17. set burst with wrap sequence diagram command 0 1 2 3 4 5 6 7 77 h cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 x x x x x x 4 x x x x x x x 5 x w6-w4 x x x x x x 6 x x x x x x x x x wp #( io 2) hold #( io 3)
25 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 18. page program sequence diagram 7. 1 5 . quad page program (32h) the quad page program command is for programming the memory using four pins: io0, io1, io2 and io3. to use quad page program the quad enable in status register bit9 must be set (qe=1). a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the quad page program command is entered by driving cs# low, followed by the command code (32h), three address bytes and at least one data byte on io pins. the command sequence is shown in figure19. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the quad page program (pp) command is not executed. as soon as cs# is driven high, the self-timed quad page program cycle (whose duration is t pp) is initiated. while the quad page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed quad page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a quad page program command applied to a page which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) is not executed.
26 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7.1 6 . fast page program (fpp) (f2h) the fast page program (fpp) command is used to program the memory. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the fast page program (fpp) command is entered by driving cs# low, followed by the command code, three address bytes and at least one data byte on si. if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). cs# must be driven low for the entire duration of the sequence. the page program command sequence: cs# goes low sending page program command 3-byte address on si at least 1 byte data on si cs# goes high. the command sequence is shown in figure20. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the fast page program (fpp) command is not executed. as soon as cs# is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the figure 19. quad page program sequence diagram command 0 1 2 3 4 5 6 7 32h cs# sclk 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address 32 33 34 35 4 0 msb 36 37 38 39 si(io0) so(io1) wp#(io2) hold#(io3) 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte1 byte2 cs# sclk si(io0) so(io1) wp#(io2) hold#(io3) 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 536 537 538 539 540 541 542 543 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte11 4 0 5 1 6 2 7 3 byte12 4 0 5 1 6 2 7 3 byte253 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte256
27 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7.1 7 . sector erase (se) (20h) the sector erase (se) command is used to erase all the data of the chosen sector. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the sector erase (se) command is entered by driving cs# low, followed by the command code, and 3-address byte on si. any address inside the sector is a valid address for the sector erase (se) command. cs# must be driven low for the entire duration of the sequence. the sector erase command sequence: cs# goes low sending sector erase command 3-byte address on si cs# goes high. the command sequence is shown in figure21. cs# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the sector erase (se) command is not executed. as soon as cs# is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) command applied to a sector which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) bit (see table1 & table1 .1 .) is not executed. page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a fast page program (fpp) command is not executed when it is applied to a page protected by the block protect (bp4, bp3, bp2, bp1, bp0). figure 20. fast page program sequence diagram figure 21. sector erase sequence diagram command 0 1 2 3 4 5 6 7 20 h cs# s cl k si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22
28 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7. 1 8 . 32kb block erase (be) (52h) the 32kb block erase (be) command is used to erase all the data of the chosen block. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the 32kb block erase (be) command is entered by driving cs# low, followed by the command code, and three address bytes on si. any address inside the block is a valid address for the 32kb block erase (be) command. cs# must be driven low for the entire duration of the sequence. the 32kb block erase command sequence: cs# goes low sending 32kb block erase command 3-byte address on si cs# goes high. the command sequence is shown in figure22. cs# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32kb block erase (be) command is not executed. as soon as cs# is driven high, the self-timed block erase cycle (whose duration is t be ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a 32kb block erase (be) command applied to a block which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) bits (see table1. & table1 .1 .) is not executed. figure 22. 32kb block erase sequence diagram command 0 1 2 3 4 5 6 7 52 h cs# s cl k si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 7.1 9 . 64kb block erase (be) (d8h) the 64kb block erase (be) command is used to erase all the data of the chosen block. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the 64kb block erase (be) command is entered by driving cs# low, followed by the command code, and three address bytes on si. any address inside the block is a valid address for the 64kb block erase (be) command. cs# must be driven low for the entire duration of the sequence. the 64kb block erase command sequence: cs# goes low sending 64kb block erase command 3-byte address on si cs# goes high. the command sequence is shown in figure23. cs# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64kb block erase (be) command is not executed. as soon as cs# is driven high, the self-timed block erase cycle (whose duration is t be ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a 64kb block erase (be) command applied to a block which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) bits (see table1. & table1 .1 .) is not executed.
29 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 23. 64kb block erase sequence diagram command 0 1 2 3 4 5 6 7 d8h cs # sc lk si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 7. 20 . chip erase (ce) (60/c7h) the chip erase (ce) command is used to erase all the data of the chip. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the chip erase (ce) command is entered by driving cs# low, followed by the command code on serial data input (si). cs# must be driven low for the entire duration of the sequence. the chip erase command sequence: cs# goes low sending chip erase command cs# goes high. the command sequence is shown in figure24. cs# must be driven high after the eighth bit of the command code has been latched in; otherwise the chip erase command is not executed. as soon as cs# is driven high, the self- timed chip erase cycle (whose duration is t ce ) is initiated. while the chip erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed chip erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the chip erase (ce) command is executed only if all block protect (bp2, bp1 and bp0) bits are 0. the chip erase (ce) command is ignored if one or more sectors are protected. figure 24. chip erase sequence diagram command 0 1 2 3 4 5 6 7 60h or c7h cs# sc lk si 7. 21 . deep power-down (dp) (b9h) executing the deep power-down (dp) command is the only way to put the device in the lowest consumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase commands. driving cs# high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) command. once the device has entered the deep power-down mode, all commands are ignored except the release from deep power-down and read device id (rdi) command. this releases the device from this mode. the release from deep power-down and read device id (rdi) command also allows the device id of the device to be output on so. the deep power-down mode automatically stops at power-down, and the device always power-up in the standby mode. the deep power-down (dp) command is entered by driving cs# low, followed by the command
30 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash code on si. cs# must be driven low for the entire duration of the sequence. the deep power-down command sequence: cs# goes low sending deep power-down command cs# goes high. the command sequence is shown in figure25. cs# must be driven high after the eighth bit of the command code has been latched in; otherwise the deep power-down (dp) command is not executed. as soon as cs# is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power- down mode is entered. any deep power-down (dp) command, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 25. deep power-down sequence diagram command 0 1 2 3 4 5 6 7 b9 h c s # s c lk si t dp stand-by mode deep power-down mode 7. 22 . release from deep power-down or high performance mode and read device id (rdi) (abh) the release from power-down or high performance mode/device id command is a multi-purpose command. it can be used to release the device from the power-down state or high performance mode or obtain the devices electronic identification (id) number. to release the device from the power-down state or high performance mode, the command is issued by driving the cs# pin low, shifting the instruction code abh and driving cs# high as shown in figure26. release from power-down will take the time duration of t res1 (see ac characteristics) before the device will resume normal operation and other command are accepted. the cs# pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the command is initiated by driving the cs# pin low and shifting the instruction code abh followed by 3-dummy byte. the device id bits are then shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure27. the device id value for the GD25Q32c is listed in manufacturer and device identification table. the device id can be read continuously. the command is completed by driving cs# high. when used to release the device from the power-down state and obtain the device id, the command is the same as previously described, and shown in figure27, except that after cs# is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other command will be accepted. if the release from power-down/device id command is issued while an erase, program or write cycle is in process (when wip equal 1) the command is ignored and will not have any effects on the current cycle. figure 26. release power-down sequence or high performance mode sequence diagram command 0 1 2 3 4 5 6 7 abh cs # sclk si res 1 stand - by mode deep power - down mode t
31 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 27. release power-down and read device id sequence diagram 7. 23 . read manufacture id/device id (rems) (90h) the read manufacturer/device id command is an alternative to the release from power-down/device id command that provides both the jedec assigned manufacturer id and the specific device id. the command is initiated by driving the cs# pin low and shifting the command code 90h followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure28. if the 24-bit address is initially set to 000001h, the device id will be read first. figure 28. read manufacture id/device id sequence diagram
32 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7. 2 4 . dual i/o read manufacture id/device id (92h) the dual i/o read manufacturer/device id command is an alternative to the release from power-down/ device id command that provides both the jedec assigned manufacturer id and the specific device id by dual i/o. the command is initiated by driving the cs# pin low and shifting the command code 92h followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure29. if the 24-bit address is initially set to 000001h, the device id will be read first. figure 29. read manufacture id/device id dual i/o sequence diagram command 0 1 2 3 4 5 6 7 92h cs# sclk si(io0) so(io1) 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 a23-16 a15-8 a7-0 m7-0 cs# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 si(io0) so(io1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 sclk mfr id device id 40 41 42 43 6 4 2 0 7 5 3 1 44 45 46 47 6 4 2 0 7 5 3 1 mfr id (repeat) device id (repeat) mfr id (repeat) device id (repeat) 7. 2 5 . quad i/o read manufacture id/device id (94h) the quad i/o read manufacturer/device id command is an alternative to the release from power-down/ device id command that provides both the jedec assigned manufacturer id and the specific device id by quad i/o. the command is initiated by driving the cs# pin low and shifting the command code 94h followed by a 24-bit address (a23-a0) of 000000h. and 4 dummy clocks. after which, the manufacturer id and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure30. if the 24-bit address is initially set to 000001h, the device id will be read first.
33 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 30. read manufacture id/device id quad i/o sequence diagram command 0 1 2 3 4 5 6 7 94h cs# sclk si(io0) so(io1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 a23-16 a15-8 a7-0 m7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 wp#(io2) hold#(io3) dummy mfr id did cs# sclk si(io0) so(io1) wp#(io2) hold#(io3) 24 25 26 27 28 29 30 31 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 mfr id (repeat) did (repeat) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 mfr id (repeat) did (repeat) 7. 26 . read identification (rdid) (9fh) the read identification (rdid) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. the device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. the read identification (rdid) command while an erase or program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. the read identification (rdid) command should not be issued while the device is in deep power-down mode. the device is first selected by driving cs# to low. then, the 8-bit command code for the command is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data output, each bit being shifted out during the falling edge of serial clock. the command sequence is shown in figure31. the read identification (rdid) command is terminated by driving cs# to high at any time during data output. when cs# is driven high, the device is put in the standby mode. once in the standby mode, the device waits to be selected, so that it can receive, decode and execute commands.
34 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 31. read identification id sequence diagram 7. 2 7 . high performance mode (hpm) (a3h) the high performance mode (hpm) command must be executed prior to dual or quad i/o commands when operating at high frequencies (see f r and f c1 in ac electrical characteristics). this command allows pre- charging of internal charge pumps so the voltages required for accessing the flash memory array are readily available. the command sequence: cs# goes low sending a3h command sending 3-dummy byte cs# goes high. see figure32. after the hpm command is executed, the device will maintain a slightly higher standby current (icc8) than standard spi operation. the release from power-down or hpm command (abh) can be used to return to standard spi standby current (icc1). in addition, power-down command (b9h) will also release the device from hpm mode back to standard spi standby state. figure 32. high performance mode sequence diagram command 0 1 2 3 4 5 6 7 a3h cs # sclk si 8 9 29 30 31 msb 2 1 0 3 dummy bytes 23 22 so high performance mode hpm t 7. 28 . program/erase suspend (pes) (75h) the program/erase suspend command 75h, allows the system to interrupt a page program or sector/ block erase operation and then read data from any other sector or block. the write status register command (01h/31h/11h) and erase/program security registers command (44h, 42h) and erase commands (20h, 52h, d8h, c7h, 60h) and page program command (02h/32h) are not allowed during program/erase suspend. program/erase suspend is valid only during the page program or sector/block erase operation. a maximum of
35 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash time of tsus (see ac characteristics) is required to suspend the program/erase operation. the program/erase suspend command will be accepted by the device only if the sus2/sus1 bit in the status register equal to 0 and wip bit equal to 1 while a page program or a sector or block erase operation is on- going. if the sus2/sus1 bit equal to 1 or wip bit equal to 0, the suspend command will be ignored by the device. the wip bit will be cleared from 1 to 0 within tsus and the sus2/sus1 bit will be set from 0 to 1 immediately after program/erase suspend. a power-off during the suspend period will reset the device and release the suspend state. the command sequence is show below. figure 33. program/erase suspend sequence diagram command 0 1 2 3 4 5 6 7 75 h cs # sclk si so high -z tsus accept read command 7. 29 . program/erase resume (per) (7ah) the program/erase resume command must be written to resume the program or sector/block erase operation after a program/erase suspend command. the program/erase command will be accepted by the device only if the sus2/sus1 bit equal to 1 and the wip bit equal to 0. after issued the sus2/sus1 bit in the status register will be cleared from 1 to 0 immediately, the wip bit will be set from 0 to 1 within 200ns and the sector or block will complete the erase operation or the page will complete the program operation. the program/erase resume command will be ignored unless a program/erase suspend is active. the command sequence is show in figure34. figure 34. program/erase resume sequence diagram command 0 1 2 3 4 5 6 7 7ah cs# sclk si so resume erase/program 7. 30 . erase security registers (44h) the GD25Q32c provides three 1024-byte security registers which can be erased and programmed individually. these registers may be used by the system manufacturers to store security and other important information separately from the main memory array. the erase security registers command is similar to sector/block erase command. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the erase security registers command sequence: cs# goes low sending erase security registers command
36 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash address a23-a16 a15-a12 a11-a10 a9-a0 security register #1 00h 0 0 0 1 0 0 byte address security register #2 00h 0 0 1 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 byte address figure 35. erase security registers command sequence diagram command 0 1 2 3 4 5 6 7 44 h cs # sclk si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 7. 31 . program security registers (42h) the program security registers command is similar to the page program command. it allows from 1 to 1024 bytes security registers data to be programmed. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the program security registers command. the program security registers command is entered by driving cs# low, followed by the command code (42h), three address bytes and at least one data byte on si. as soon as cs# is driven high, the self-timed program security registers cycle (whose duration is t pp ) is initiated. while the program security registers cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed program security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. if the security registers lock bit (lb3-1) is set to 1, the security registers will be permanently locked. program security registers command will be ignored. address a23-a16 a15-a12 a11-a10 a9-a0 security register #1 00h 0 0 0 1 0 0 byte address security register #2 00h 0 0 1 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 byte address cs# goes high. the command sequence is shown in figure35. cs# must be driven high after the eighth bit of the command code has been latched in; otherwise the erase security registers command is not executed. as soon as cs# is driven high, the self-timed erase security registers cycle (whose duration is t se ) is initiated. while the erase security registers cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed erase security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the security registers lock bit (lb3-1) in the status register can be used to otp protect the security registers. once the lb bit is set to 1, the security registers will be permanently locked; the erase security registers command will be ignored.
37 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure 36. program security registers command sequence diagram command 0 1 2 3 4 5 6 7 42 h cs # sclk si 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 6 5 4 3 2 1 0 7 cs # sclk si msb data byte 2 32 33 34 35 7 6 5 4 3 2 1 0 msb 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 data byte 1 data byte 3 data byte 256 msb msb msb 36 37 38 39 2072 2073 2074 2075 2076 2077 2078 2079 7. 3 2 . read security registers (48h) the read security registers command is similar to fast read command. the command is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency f c , during the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. once the a9-a0 address reaches the last byte of the register (byte 3ffh), it will reset to 000h, the command is completed by driving cs# high. address a23-a16 a15-a12 a11-a10 a9-a0 security register #1 00h 0 0 0 1 0 0 byte address security register #2 00h 0 0 1 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 byte address figure 37. read security registers command sequence diagram command 0 1 2 3 4 5 6 7 48 h cs # sclk si so high -z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address msb 34 35 36 37 33 6 5 4 3 2 1 0 38 39 data out 1 32 42 43 44 45 41 46 47 40 7 6 5 4 3 2 1 0 7 6 5 7 data out 2 cs # sclk si so msb dummy byte
38 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 7. 3 4 . read serial flash discoverable parameter (5ah) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. sfdp is a standard of jedec standard no.216. 7. 33 . enable reset (66h) and reset (99h) if the reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as volatile status register bits, write enable latch status (wel), program/erase suspend status, read parameter setting (p7-p0), continuous read mode bit setting (m7-m0) and wrap bit setting (w6-w4). the reset (99h) command sequence as follow: cs# goes low sending enable reset command cs# goes high cs# goes low sending reset command cs# goes high. once the reset command is accepted by the device, the device will take approximately t rst =60 s to reset. during this period, no command will be accepted. data corruption may happen if there is an on-going or suspended internal erase or program operation when reset command sequence is accepted by the device. it is recommended to check the busy bit and the sus bit in status register before issuing the reset command sequence. figure 38. enable reset and reset command sequence diagram figure 38. enable reset and reset command sequence diagram 7.34. read serial flash discoverable parameter (5ah) figure 39. read serial flash discoverable parameter command sequence diagram figure 39. read serial flash discoverable parameter command sequence diagram
39 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash table3. signature and parameter identification data values description comment add(h) (byte) dw add (bit) data data sfdp signature fixed:50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdf minor revision number start from 00h 04h 07:00 00h 00h sfdf major revision number start from 01h 05h 15:08 01h 01h number of parameters headers start from 00h 06h 23:16 01h 01h unused contains 0ffh and can never be changed 07h 31:24 ffh ffh id n umber (jedec) 00h: it indicates a jedec specified header 08h 07:00 00h 00h parameter table minor revision number start from 000h 09h 15:08 00h 00h parameter table major revision number start from 001h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) fist address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused contains 0ffh and can never be changed 0fh 31:24 ffh ffh id number (elm manufacturer id) it is indicates elm manufacturer id 10h 07:00 c8h c8h parameter table minor revision number start from 000h 11h 15:08 00h 00h parameter table major revision number start from 001h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 03h 03h parameter table pointer (ptp) fist address of elm flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused contains 0ffh and can never be changed 17h 31:24 ffh ffh
40 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash table4. parameter table (0): jedec flash parameter tables description comment add(h) (byte) dw add (bit) data data block/sector erase size 00: reserved; 01: 4kb erase; 10: reserved; 11: not support 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction requested for writing to volatile status registers 0: nonvolatile status bit 1: volatile status bit (bp status register bit) 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode, note: if target flash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read 0=not support, 1=support 32h 16 1 b f1h address bytes number used in addressing flash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 00b double transfer rate (dtr) clocking 0=not support, 1=support 19 0b (1-2-2) fast read 0=not support, 1=support 20 1b (1-4-4) fast read 0=not support, 1=support 21 1b (1-1-4) fast read 0=not support, 1=support 22 1b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 01ffffffh (1-4-4) fast read number of wait states 00000b: wait states (dummy clocks) not support 38h 04:00 00100b 44h (1-4-4) fast read number of mode bits 000b: mode bits not support 07:05 010b (1-4-4) fast read opcode 39h 15:08 ebh ebh (1-1-4) fast read number of wait states 00000b: wait states (dummy clocks) not support 3ah 20:16 01000b 08h (1-1-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-1-4) fast read opcode 3bh 31:24 6bh 6bh (1-1-2) fast read number of wait states 00000b: wait states (dummy clocks) not support 3ch 04:00 01000b 08h (1-1-2) fast read number of mode bits 000b: mode bits not support 07:05 000b (1-1-2) fast read opcode 3dh 15:08 3bh 3bh
41 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash description comment add(h) (byte) dw add (bit) data data (1-2-2) fast read number of wait states 00000b: wait states (dummy clocks) not support 3eh 20:16 00010b 42h (1-2-2) fast read number of mode bits 000b: mode bits not support 23:21 010b (1-2-2) fast read opcode 3fh 31:24 bbh bbh (2-2-2) fast read 0=not support; 1=support 40h 00 0b eeh unused 03:01 111b (4-4-4) fast read 0=not support; 1=support 04 0b unused 07:05 111b unused 43h:41h 31:0 8 0 ffh 0 ffh unused 45h:44h 15 :0 0 0 ffh 0 ffh (2-2-2) fast read number of wait states 00000b: wait states (dummy clocks) not support 46h 20:16 00000b 00h (2-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15 : 00 0 ffh 0 ffh (4-4-4) fast read number of wait states 00000b: wait states (dummy clocks) not support 4ah 20:16 00000b 00h (4-4-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (4-4-4) fast read opcode 4bh 31:24 ffh ffh sector type 1 size sector/block size=2^n bytes 0 00b: this sector type dont exist 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size=2^n bytes 0 00b: this sector type dont exist 4eh 23:16 0fh 0fh sector type 2 erase opcode 4fh 31:24 52h 52h sector type 3 size sector/block size=2^n bytes 0 00b: this sector type dont exist 50h 07:00 10h 10h sector type 3 erase opcode 51h 15:08 d8h d8h sector type 4 size sector/block size=2^n bytes 0 00b: this sector type dont exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh
42 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash table5. parameter table (1): elm flash parameter tables description comment add(h) (byte) dw add (bit) data data vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 15 :00 3600h 3600h vcc supply minimum voltage 1650h=1.650v 2250h=2.250v 2350h=2.350v 2700h=2.700v 63h:62h 31:16 27 00h 27 00h hw reset# pin 0=not support; 1=support 65h:64h 00 0b f99eh hw hold# pin 0=not support; 1=support 01 1b deep power down mode 0=not support; 1=support 02 1b sw reset 0=not support; 1=support 03 1b sw reset opcode should be issue reset enable(66h) before reset cmd. 11:04 1001 1001b (99h) program suspend/resume 0=not support; 1=support 12 1b erase suspend/resume 0=not support; 1=support 13 1b unused 14 1b wrap-around read mode 0=not support; 1=support 15 1b wrap-around read mode opcode 66h 23:16 77h 77h wrap-around read data length 08h: support 8b wrap-around read 16h: 8b & 16b 32h: 8b & 16b & 32b 64h: 8b & 16b & 32b & 64b 67h 31:24 64h 64h individual block lock 0=not support; 1=support 6bh:68h 00 0b ebfch individual block lock bit (volatile/nonvolatile) 0=volatile; 1=nonvolatile 01 0b individual block lock opcode 09:02 ffh individual block lock volatile protect bit default protect status 0=protect; 1=unprotect 10 0b secured otp 0=not support; 1=support 11 1b read lock 0=not support; 1=support 12 0b permanent lock 0=not support; 1=support 13 1b unused 15:14 11b unused 31:16 ffffh ffffh
43 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 8.1 . power-on timing symbol parameter min max unit tvsl vcc(min) to cs# low 10 us tpuw time delay from vcc(min) to write instruction 1 10 ms vwi write inhibit voltage vcc(min) 1 2.5 v table6. power-up timing and write inhibit threshold 8. electrical characteristics 8 . 2 . initial delivery state the device is delivered with the memory array erased: all bits are set to 1(each byte contains ffh).the status register bits are set to 0, except drv0 bit (s21) is set to 1. 8 . 3 . data retention and endurance parameter test condition min unit minimum pattern data retention time 150c 10 years 125c 2 0 years erase/program endurance -40 to 85c 100k cycles figure 40. power-on timing sequence diagram
44 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 8 . 4 . absolute maximum ratings parameter value unit ambient operating temperature -40 to 85 c storage temperature -65 to 150 c output short circuit current 200 ma applied input/output voltage -0.6 to vcc+4.0 v transient input/output voltage(note: overshoot) -2.0 to vcc+2.0 v v cc -0.6 to vcc+4.0 v 8 . 5 . capacitance measurement conditions symbol parameter min typ max unit conditions cin input capacitance 6 pf vin=0v cout output capacitance 8 pf vout=0v c l load capacitance 30 pf input rise and fall time 5 ns input pulse voltage 0.1vcc to 0.8vcc v input timing reference voltage 0.2vcc to 0.7vcc v output timing reference voltage 0.5vcc v figure 41. maximum negative/positive overshoot diagram maximum negative overshoot waveform maximum positive overshoot waveform vss 20ns 20ns 20ns vss-2.0v vc c 20ns 20ns 20ns vcc + 2.0v figure 42. input test waveform and measurement level diagram 0.8v cc 0.1v cc 0.7v cc 0.2v cc 0.5v cc ac measurement level i nput timing reference level output timing re f erence level note : input pulse rise and fall time are <5ns
45 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 8. 6 . dc characteristics symbol parameter test condition min. typ. max. unit. i li input leakage current 2 a i l o output leakage current 2 a i cc1 standby current cs#=vcc, v in =vcc or vss 1 5 a i cc 2 deep power-down current cs#=vcc, v in =vcc or vss 1 5 a i cc 3 operating current (read) clk=0.1vcc/0.9vcc at 120mhz, q=open(*1,*2,*4 i/o) 15 20 ma clk=0.1vcc/0.9vcc at 80mhz, q=open(*1,*2,*4 i/o) 13 18 ma i cc 4 operating current (pp) cs#=vcc 20 ma i cc 5 operating current (wrsr) cs#=vcc 20 ma i cc 6 operating current (se) cs#=vcc 20 ma i cc 7 operating current (be) cs#=vcc 20 ma i cc 8 operating current (ce) cs#=vcc 20 ma i cc 9 high performance current 400 8 00 a v i l input low voltage -0.5 0.2vcc v v i h input high voltage 0.7vcc vcc+0.4 v v ol output low voltage i ol = 100 a 0.2 v v o h output high voltage i oh =-100 a vcc-0.2 v (t= -40 c ~85 c , vcc=2.7~3.6v ) 8. 7 . ac characteristics (t= -40 c ~85 c , vcc=2.7~3.6v, c l =30pf) symbol parameter min. typ. max. unit. f c serial clock frequency for: dual i/o(bbh), quad i/o(ebh), quad output(6bh) (dual i/o & quad i/o without high performance mode), on 3.0v-3.6v power supply dc. 104 mhz f c1 serial clock frequency for: dual i/o(bbh), quad i/o(ebh), quad output(6bh) (dual i/o & quad i/o without high performance mode), on 2.7v-3.0v power supply dc. 80 mhz f c2 serial clock frequency for: dual i/o(bbh), quad i/o(ebh), quad output(6bh) (dual i/o & quad i/o with high performance mode), on 2.7v-3.6v power supply dc. 120 mhz f r serial clock frequency for: read (03h) dc. 80 mhz t clh serial clock high time 4 ns t c ll serial clock low time 4 ns t clc h serial clock rise time (slew rate) 0.2 v/ns t chc l serial clock fall time (slew rate) 0.2 v/ns t slc h cs# active setup time 5 ns t chsh cs# active hold time 5 ns
46 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash note: (1). max value 4kb t se with<50k cycles is 200ms and >50k & <100k cycles is 300ms. (2). max value 32kb t be with<50k cycles is 0.8s and >50k & <100k cycles is 1.6s. (3). max value 64kb t be with<50k cycles is 1.2s and >50k & <100k cycles is 2.0s. symbol parameter min. typ. max. unit. t s h ch cs# not active setup time 5 ns t c h sl cs# not active hold time 5 ns t shsl cs# high time (read/write) 20 ns t sh qz output disable time 6 ns t cl q x output hold time 1.2 ns t dvch data in setup time 2 ns t chdx data in hold time 2 ns t hlch hold# low setup time (relative to clock) 5 ns t hhch hold# high setup time (relative to clock) 5 ns t chhl hold# high hold time (relative to clock) 5 ns t chh h hold# low hold time (relative to clock) 5 ns t hl qz hold# low to high-z output 6 ns t h h q x hold# high to low-z output 6 ns t clq v clock low to output valid 7 ns t whsl write protect setup time before cs# low 20 ns t s hwl write protect hold time after cs# high 100 ns t dp cs# high to deep power-down mode 20 s t res1 cs# high to standby mode without electronic signature read 20 s t res 2 cs# high to standby mode with electronic signature read 20 s t sus cs# high to next command after suspend 20 s t rst cs# high to next command after reset 20 s t w write status register cycle time 5 3 0 ms t bp1 byte program time (first byte) 30 50 s t bp2 additional byte program time (after first byte) 2.5 12 s t pp page programming time 0.6 2.4 ms t se sector erase time (4k bytes) 5 0 200/300(1) ms t be1 block erase time (32k bytes) 0.15 0.8/1.6(2) s t be 2 block erase time (64k bytes) 0.25 1.2/2.0(3) s t ce chip erase time (GD25Q32c) 15 30 s
47 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash figure43. serial input timing diagram sclk cs# si msb so high-z lsb tchsl tslch tdvch tchdx tshch tchsh tchcl tclch tshsl figure44. output timing diagram cs # sclk so si least significant address bit ( lib ) in tclqv tclqx tclqx tclqv tclh tcll tshqz lsb figure45. hold timing diagram cs # sclk so hold # tchhl thlqz thlch tchhh thhch thhqx si do not care during hold operation .
48 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 9 . ordering information packing type y: tray r: tape & reel green code g: pb free & haloge n free green package s: pb free & haloge n free green package srp1 available temperature range i: industrial(-40 c to +85 c) package type s : sop8 208mil w: wson8 (6 5mm) generation c : version density 32 : 3 2mb series q : 3v, 4kb uniform sector product family 25 : spi interface flash gd 25 q 32 c x i g x
49 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 10.1 package sop8 208mil 10 . package information 1 4 5 8 e1 e d a a2 a1 e b l l1 c ? symbol a a1 a2 b c d e e1 e l l1 unit mm min - 0.05 1.70 0.31 0.18 5.13 7.70 5.18 - 0.50 1.21 0 nom - 0.15 1.80 0.41 0.21 5.23 7.90 5.28 1.27bsc 0.67 1.31 5 max 2.16 0.25 1.91 0.51 0.25 5.33 8.10 5.38 - 0.85 1.41 8 inch min - 0.002 0.067 0.012 0.007 0.202 0.303 0.204 - 0.020 0.048 0 nom - 0.006 0.071 0.016 0.008 0.206 0.311 0.208 0.050bsc 0.026 0.052 5 max 0.085 0.010 0.075 0.020 0.010 0.210 0.319 0.212 - 0.033 0.056 8 dimensions note: both package length and width do not include mold flash.
50 r ev.1. 0 50 - http://www.elm-tech.com GD25Q32cxigx 3.3v uni form sector dual and quad serial flash 10.2 package wson8 ( 6 5 mm) symbol a a1 a2 b d d1 e e1 e y l unit mm min 0.70 - 0.19 0.35 5.90 3.25 4 .90 3 .85 - 0.00 0.50 nom 0.75 - 0.22 0.42 6.00 3.37 5 .00 3.97 1.27 bsc 0.04 0.60 max 0.80 0.05 0.25 0.48 6.10 3.50 5 .10 4.10 - 0.08 0.75 inch min 0.028 - 0.007 0.014 0.232 0.128 0.193 0.151 - 0.000 0.020 nom 0.030 - 0.009 0.016 0.236 0.133 0.197 0.156 0.05 bsc 0.001 0.024 max 0.032 0.002 0.010 0.019 0.240 0.138 0.201 0.161 - 0.003 0.030 dimensions note: 1. both package length and width do not include mold flash. 2. the exposed metal pad area on the bottom of the package is connected to device ground (gnd pin), so both floating and connecting gnd of exposed pad are also available. d e top view d1 e1 b e bottom view l 1 a2 a1 a side view y

▲Up To Search▲

Price & Availability of GD25Q32

	To Download GD25Q32 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .